bugfix: fix -skip_gate_cloning applied incorrectly

Signed-off-by: Kareem Farid <[email protected]>
efabless · Nov 10, 2024 · 16b6aa1 · 16b6aa1
1 parent df9dc00
commit 16b6aa1
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Showing 4 changed files with 33 additions and 13 deletions.
diff --git a/Changelog.md b/Changelog.md
@@ -14,6 +14,20 @@
 ## Documentation
 -->
 
+# 2.2.6
+
+## Steps
+
+* `OpenROAD.ResizerTimingPostGRT`
+
+  * Fixed `GRT_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead 
+  of setup fixing.
+
+* `OpenROAD.ResizerTimingPostCTS`
+
+  * Fixed `PL_RESIZER_GATE_CLONING` incorrectly applied to hold fixing instead 
+  of setup fixing.
+
 # 2.2.5
 
 ## Steps

diff --git a/openlane/scripts/openroad/rsz_timing_postcts.tcl b/openlane/scripts/openroad/rsz_timing_postcts.tcl
@@ -29,9 +29,15 @@ source $::env(SCRIPTS_DIR)/openroad/common/set_rc.tcl
 estimate_parasitics -placement
 
 # Resize
-repair_timing -verbose -setup \
-    -setup_margin $::env(PL_RESIZER_SETUP_SLACK_MARGIN) \
-    -max_buffer_percent $::env(PL_RESIZER_SETUP_MAX_BUFFER_PCT)
+set arg_list [list]
+lappend arg_list -verbose
+lappend arg_list -setup
+lappend arg_list -setup_margin $::env(PL_RESIZER_SETUP_SLACK_MARGIN)
+lappend arg_list -max_buffer_percent $::env(PL_RESIZER_SETUP_MAX_BUFFER_PCT)
+if { $::env(PL_RESIZER_GATE_CLONING) != 1 } {
+    lappend arg_list -skip_gate_cloning
+}
+repair_timing {*}$arg_list
 
 set arg_list [list]
 lappend arg_list -verbose
@@ -42,9 +48,6 @@ lappend arg_list -max_buffer_percent $::env(PL_RESIZER_HOLD_MAX_BUFFER_PCT)
 if { $::env(PL_RESIZER_ALLOW_SETUP_VIOS) == 1 } {
     lappend arg_list -allow_setup_violations
 }
-if { $::env(PL_RESIZER_GATE_CLONING) != 1 } {
-    lappend arg_list -skip_gate_cloning
-}
 repair_timing {*}$arg_list
 
 # Legalize

diff --git a/openlane/scripts/openroad/rsz_timing_postgrt.tcl b/openlane/scripts/openroad/rsz_timing_postgrt.tcl
@@ -32,9 +32,15 @@ source $::env(SCRIPTS_DIR)/openroad/common/grt.tcl
 estimate_parasitics -global_routing
 
 # Resize
-repair_timing -verbose -setup \
-    -setup_margin $::env(GRT_RESIZER_SETUP_SLACK_MARGIN) \
-    -max_buffer_percent $::env(GRT_RESIZER_SETUP_MAX_BUFFER_PCT)
+set arg_list [list]
+lappend arg_list -verbose
+lappend arg_list -setup
+lappend arg_list -setup_margin $::env(GRT_RESIZER_SETUP_SLACK_MARGIN)
+lappend arg_list -max_buffer_percent $::env(GRT_RESIZER_SETUP_MAX_BUFFER_PCT)
+if { $::env(GRT_RESIZER_GATE_CLONING) != 1 } {
+    lappend arg_list -skip_gate_cloning
+}
+repair_timing {*}$arg_list
 
 set arg_list [list]
 lappend arg_list -verbose
@@ -45,9 +51,6 @@ lappend arg_list -max_buffer_percent $::env(GRT_RESIZER_HOLD_MAX_BUFFER_PCT)
 if { $::env(GRT_RESIZER_ALLOW_SETUP_VIOS) == 1 } {
     lappend arg_list -allow_setup_violations
 }
-if { $::env(GRT_RESIZER_GATE_CLONING) != 1 } {
-    lappend arg_list -skip_gate_cloning
-}
 repair_timing {*}$arg_list
 
 # Re-DPL and GRT

diff --git a/pyproject.toml b/pyproject.toml
@@ -1,6 +1,6 @@
 [tool.poetry]
 name = "openlane"
-version = "2.2.5"
+version = "2.2.6"
 description = "An infrastructure for implementing chip design flows"
 authors = ["Efabless Corporation and Contributors <[email protected]>"]
 readme = "Readme.md"