[LTO] Override TargetABI from module flags if present when creating T…

[kito-cheng]

…argetMachine

RISC-V's data layout is also determined by the ABI, not only the target triple, however the TargetMachine is created with the target triple's data layout, that is not always correct. This patch changes the TargetMachine's data layout to the one specified in the module flags if present.

The same problem will happen with other targets like MIPS, but unfortunately, MIPS didn't emit the target-abi into the module flags, so this patch only fixes the issue for RISC-V.

NOTE: MIPS with -mabi=n32 can trigger the same issue.

Another possible solution is add new parameter to the TargetMachine constructor, but that would require changes in all the targets.

[llvmbot]

@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-lld
@llvm/pr-subscribers-lto

@llvm/pr-subscribers-lld-elf

Author: Kito Cheng (kito-cheng)

Changes

…argetMachine

RISC-V's data layout is also determined by the ABI, not only the target triple, however the TargetMachine is created with the target triple's data layout, that is not always correct. This patch changes the TargetMachine's data layout to the one specified in the module flags if present.

The same problem will happen with other targets like MIPS, but unfortunately, MIPS didn't emit the target-abi into the module flags, so this patch only fixes the issue for RISC-V.

NOTE: MIPS with -mabi=n32 can trigger the same issue.

Another possible solution is add new parameter to the TargetMachine constructor, but that would require changes in all the targets.

---

Full diff: https://github.com/llvm/llvm-project/pull/126497.diff

2 Files Affected:

• (added) lld/test/ELF/lto/riscv-ilp32e.ll (+25)
• (modified) llvm/lib/LTO/LTOBackend.cpp (+11-1)

diff --git a/lld/test/ELF/lto/riscv-ilp32e.ll b/lld/test/ELF/lto/riscv-ilp32e.ll
new file mode 100644
index 000000000000000..ea2b57d48335865
--- /dev/null
+++ b/lld/test/ELF/lto/riscv-ilp32e.ll
@@ -0,0 +1,25 @@
+; REQUIRES: riscv
+;
+; Check that we don't crash on DataLayout incompatibility issue.
+;
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t.elf
+; RUN: llvm-readobj -h %t.elf | FileCheck %s --check-prefixes=CHECK
+;
+; CHECK:  Machine: EM_RISCV (0xF3)
+; CHECK:  EF_RISCV_RVE (0x8)
+
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S32"
+target triple = "riscv32-unknown-unknown-elf"
+
+define dso_local i32 @_start() #0 {
+entry:
+  ret i32 0
+}
+
+attributes #0 = { "target-cpu"="generic-rv32" "target-features"="+32bit,+e" }
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 1, !"target-abi", !"ilp32e"}
diff --git a/llvm/lib/LTO/LTOBackend.cpp b/llvm/lib/LTO/LTOBackend.cpp
index 8a2dddce4892c1a..b9d2242d4a2cf46 100644
--- a/llvm/lib/LTO/LTOBackend.cpp
+++ b/llvm/lib/LTO/LTOBackend.cpp
@@ -221,8 +221,18 @@ createTargetMachine(const Config &Conf, const Target *TheTarget, Module &M) {
   else
     CodeModel = M.getCodeModel();
 
+  TargetOptions TargetOpts = Conf.Options;
+
+  if (TargetOpts.MCOptions.ABIName.empty()) {
+    Metadata *ABI = M.getModuleFlag("target-abi");
+    if (ABI) {
+      const StringRef &ModABI = cast<MDString>(ABI)->getString();
+      TargetOpts.MCOptions.ABIName = ModABI;
+    }
+  }
+
   std::unique_ptr<TargetMachine> TM(TheTarget->createTargetMachine(
-      TheTriple, Conf.CPU, Features.getString(), Conf.Options, RelocModel,
+      TheTriple, Conf.CPU, Features.getString(), TargetOpts, RelocModel,
       CodeModel, Conf.CGOptLevel));
 
   assert(TM && "Failed to create target machine");

[teresajohnson]

Given that this isn't an lld change, the test should be in LLVM not lld. Take a look at llvm/test/LTO/X86/codemodel-1.ll for an example, and the LTO subdirectory presumably needs a RISCV subdirectory.

[teresajohnson]

I'm not sure what the current status is of PR100833, but note it adds a facility to get this module flag to Module.h. Consider adding that here so they are commoned.

[kito-cheng]

#100833 seems need few more days, will rebase and use that once that patch landed.

[kito-cheng]

Changes:

• Move test file from lld/test/ELF/lto to llvm/test/LTO/RISCV